The present invention relates to a data signal line driving circuit and an image display apparatus having a shift register circuit for transmitting a pulse signal in sync with a clock signal.
A liquid crystal display device adopting an active matrix driving method has been known as an example image display apparatus. The liquid crystal display device adopting the above driving method is composed of a pixel array, a data signal line driving circuit, and a scanning signal line driving circuit.
A plurality of scanning signal lines and a plurality of data signal lines are provided in the pixel array to cross each other, and a pixel is provided to each area enclosed by two adjacent scanning signal lines and two adjacent data signal lines, thereby forming a matrix arrangement.
Each pixel is composed of, for example, an electric field effect transistor serving as a switching element, a liquid crystal capacitance, and an auxiliary capacitance. An image is displayed as transmittance of the liquid crystal in each pixel varies with the ON/OFF action of the electric field effect transistor at the timing of a signal supplied to the scanning signal lines, while a voltage is applied to the liquid crystal capacitance and auxiliary capacitance by a signal supplied to the data signal lines.
Incidentally, a conventional active matrix liquid crystal display device generally uses an amorphous silicon thin film formed over a transparent substrate as a substrate material for a pixel transistor, and the data signal line driving circuit and scanning signal line driving circuit are composed of outboard ICs.
In contrast, to meet an increasing demand for an upgraded drivability of the pixel transistor for a larger-scale screen, cost reduction for the driving IC packaging, or packaging reliability, there has been proposed a display apparatus in which the pixel array and driving circuits are formed monlithically out of a polycrystalline silicon thin film. To further upsize the screen and reduce the costs, it is also Proposed to make elements out of the polycrystalline silicon thin film formed over the glass substrate at a process temperature up to the glass distortion point (about 600xc2x0 C.).
An example liquid crystal display device of the above monolithic structure includes a dielectric substrate having thereon formed the pixel array, data signal line driving circuit, and scanning signal line driving circuit.
Incidentally, the data signal line driving circuit has two driving methods: a dot sequential driving method and a line sequential driving method, and what distinguishes one method from the other is how a video signal is written into the data signal lines.
For example, as shown in FIG. 15, a data signal line driving circuit 122 adopting the dot sequential driving method is composed of a plurality of serially connected latch circuits LTi (i=1, 2, . . . , m), buffers BFi (i=1, 2, . . . , m) respectively connected to the output terminals of the latch circuits LTi, and analog switches ASi (i=1, 2, . . . , m) for sampling a data signal DAT from a video signal line.
The data signal DAT is inputted into the above-arranged data signal line driving circuit 122 through the video signal line as a video signal. Then, in the data signal line driving circuit 122, each analog switch ASi is opened/closed in sync with a pulse signal outputted from the corresponding latch circuit LTi through the corresponding buffer BFi in sync with a clock signal CK and a start signal SP, whereby the data signal DAT supplied from the video signal line is sampled and written into the corresponding data signal line SLi (i=1, 2, . . . ,m).
Also, as shown in FIG. 16, in a scanning signal line driving circuit 123, the output terminals of latch circuits LTj (j=1, 2, . . . , n) are respectively connected to buffers BFj (j=1, 2, . . . , n), the output terminals of the buffers BFj are respectively connected to logic circuits LGj (j=1, 2, . . . , n), and the output terminals of the logic circuits LGj are respectively connected to the buffers BFj.
Each logic circuit LGj receives a pulse signal GPS from a pulse signal line and a pulse signal outputted from the corresponding latch circuit LTj through the corresponding buffer BFj, and performs a logical operation using these two signals. Then, each logic circuit LGj outputs the operation result to a corresponding scanning signal line GLj (j=1, 2, . . . , n) as a control signal for determining whether the data signal DAT from the data signal line driving circuit 122 should be sampled or not.
As has been explained, both the data signal line driving circuit 122 and scanning signal line driving circuit 123 use the scanning circuit for sequentially transmitting the pulse signal in sync with the clock signal. A shift register circuit, a decoder circuit and the like can be used as the scanning circuit. However, the shift register circuit is generally used because it has fewer input terminals and a smaller circuit size (fewer transistors).
The shift register circuit is composed of, for example, two clocked inverters and one inverter. The two clocked inverters receive an antiphase clock signal.
Incidentally, in the scanning circuit used in each driving circuit, only one pulse signal is scanned normally, and the power consumption for transmitting the pulse signal is small.
However, in case of an image display apparatus whose scanning circuit is composed of a shift register circuit having a great number of stages, for example, in case of an image display apparatus using a VGA (Video Graphics Array) panel, the data signal line driving circuit and scanning signal line driving circuit demand a 640-stage shift register circuit and a 480-stage shift register circuit, respectively. Further, in case of an image display apparatus using an XGA (Extended Video Graphics Array) panel, the data signal line driving circuit and scanning signal line driving circuit demand a 1024-stage shift register circuit and a 768-stage register circuit, respectively.
Thus, when the scanning circuit is used for the driving circuit that drives the VGA panel or XGA panel, a sum of an input capacitance from a clock signal line of each clocked inverter in the shift register circuit becomes so large that it accounts for most of the consumed power.
Particularly, when the scanning circuit is composed of the polycrystalline silicon thin film transistor as previously mentioned, the performance (carrier mobility, threshold voltage, element voltage withstand, etc.) of the transistor is inferior to the performance of the transistor formed on a monocrystal silicon substrate, provided that both are of the same size. Thus, to improve the performance of the polycrystalline silicon thin film transistor to the same level as the performance of the transistor formed on the monocrystal silicon substrate, the element size (channel length and channel width) must be increased than the transistors on the monocrystal silicon substrate, and a high driving voltage must be supplied. Therefore, the power consumed on the clock signal line increases remarkably.
To solve the above problem, an example liquid crystal display device adopting the dot sequential driving method as shown in FIG. 17 is disclosed in, for example, Japanese Examined Patent Publication No. 50717/1988 (Tokukoushou No. 63-50717). To be more specific, the shift register circuit in the data signal line driving circuit is divided into a plurality of blocks, and the blocks are sequentially selected at regular time intervals, one at each interval, so that a clock signal CLK is supplied to the latch circuits in the selected block alone.
The above arrangement seems effective to reduce power consumption on the clock signal line if an adequate measure is taken to transmit the pulse signal among the blocks normally. Because the clock signal is selectively transmitted only to the block including latch circuits near the latch circuit to which the pulse signal is transmitted, the number of the latch circuits receiving the clock signal simultaneously is reduced, thereby saving the power consumed to drive a parasitic capacitance (an input gate capacitance of the shift register circuit, a wire capacitance, etc.) of the clock signal line (an internal clock signal line connected to a signal input section of each block inside the shift register circuit) remarkably.
However, according to the arrangement disclosed in the above publication, the timing between the video signal and clock signal may possibly be shifted from each other (time difference may be generated).
In other words, in the above-arranged data signal line driving circuit, the shift register circuit is divided into a plurality of blocks each composed of a certain number of latch circuits, and the blocks are selected sequentially at regular time intervals, one at each interval, so that the clock signal is supplied to the selected block alone. Therefore, a load applied on the clock signal line from the external is so small that the clock signal line hardly causes a delay between the first block (the closest block to the signal input section) and the last block (the remotest block from the signal input section).
In contrast, the video signal line is not divided at all, and is connected to a plurality of analog switches ASW serving as sampling switches. Thus, the load applied thereon is large enough to cause a delay between the first video signal (the closest to the signal input section) and the last video signal (the remotest from the signal input section).
FIG. 18 shows the waveforms of an external clock signal at the points G1 and Gn on an external clock signal line, the waveforms of a n internal clock signal at the points I1 and In on an internal clock signal line, and the waveforms of the video signal at the points V1 and Vn on the video signal line, which respectively correspond to a clock signal control circuit CRL1 in the first stage and a clock signal control circuit CRLn in the last stage in the data signal line driving circuit of FIG. 17. In other words, FIG. 18 shows a comparison result of the waveform of an external clock signal CLK, the waveform of an internal clock signal CKI outputted from the clock signal control circuit CRL, and the waveform of a video signal VIDEO transmitted as the data signal.
In the drawing, CKG1 indicates the waveform at the point G1 on the external clock signal line; CKI1 indicates the waveform at the point I1 on the internal clock signal line; CKGn indicates the waveform at the point Gn on the external clock signal line; CKIn indicates the waveform at the point In on the internal clock signal line; V1 indicates the waveform at the point V1 on the video signal line; and Vn indicates the waveform at the point Vn on the video signal line.
It is apparent from FIG. 18 that in the remote blocks from the signal input section, the delay is larger in the video signal than in the clock signal. The comparison between the waveform at the point In on the internal clock signal line and the waveform at the point vn on the video signal line reveals that their rising timings shift from each other. Thus, in the remote block from the signal input section, if the video signal is sampled based on the clock signal, the reproduced video causes unwanted blur or ghost, thereby making it impossible to obtain a normal video.
It is therefore an object of the present invention to provide a data signal line driving circuit which can reduce the power consumption on the clock signal line and prevent the time difference (shift in timing) between the clock signal and data signal. Also, it is another object of the present invention to provide an image display apparatus which consumes less power and can display a satisfactory image by employing the above data signal line driving circuit.
To fulfill the above objects, a data signal line driving circuit of the present invention comprises:
a shift register circuit, composed of a plurality of serially connected latch circuits, for sequentially transmitting a pulse signal in sync with a clock signal; and
an output circuit for sequentially outputting data signals to data signal lines in sync with output signals outputted from the shift register circuit,
and the above data signal line driving circuit is characterized in that:
the shift register circuit is divided into a plurality of blocks; and
stage numbers of the latch circuits in each block is set in such a manner to minimize time difference between the output signals outputted from each block and the data signal.
According to the above arrangement, unlike the conventional data signal line driving circuit, the stage numbers of the latch circuits included in each block is set in such a manner to minimize time difference between an output signal outputted from each block and the data signal. For example, when the output circuit includes an analog switch for outputting the data signal inputted from an external, the shift register circuit is arranged in such a manner that the stage numbers of the latch circuits in each block is increased monotonously with a distance from the signal input side. Accordingly, the time difference between the output signal and the data signal is minimized. Consequently, a satisfactory video can be displayed without unwanted blur or ghost caused by the above shift.
In addition, in the above arrangement, the clock signal can be supplied to each block. However, it is preferable to provide a control section for controlling the supply of the clock signal to each block, so that each block has a supply period during which the clock signal is supplied and a non-supply period during which the clock signal is not supplied. However, the supply period is set to cover at least an interval during which any of the latch circuits in its own block transmits the pulse signal.
According to the above arrangement, no clock signal is supplied to each block during the non-supply period while the pulse signal is not transmitted. Thus, the number of the latch circuits receiving the clock signal simultaneously can be reduced. Consequently, the power consumed for driving the internal clock signal lines connected to the input section inside the shift register circuit can be reduced significantly. Hence, the power consumption of the data signal line driving circuit can reduced.
Here, the power consumption of the data signal line driving circuit can be reduced to some extent if the non-supply period is provided to each block regardless of the arrangement of the non-supply period. However, to reduce the power consumption, it is preferable that the clock signal is selectively supplied only to the block including latch circuits near the latch circuit to which the pulse signal is transmitted, for example, a block including the latch circuit to which the pulse signal is transmitted and some latch circuits in the preceding stages. According to the above arrangement, the number of the latch circuits receiving the clock signal simultaneously can be minimized without causing any trouble in the shift register circuit. Consequently, the power consumption of the data signal line driving circuit can be reduced further.
Also, when the clock signal is selectively supplied, the supply period for each block may overlap or may be separated. However, when the supply period for each block do not overlap at all, either the rising or falling edge of the transmission signal can not be transmitted.
Thus, a generating circuit for generating the non-transmitted edge based on the transmitted other edge must be provided additionally, thereby upsizing the data signal line driving circuit.
Thus, it is more preferable to control the supply of the clock signals in such a manner that the clock signals respectively inputted into the latch circuits in the adjacent blocks are supplied to overlap one on the other More specifically, it is preferable to supply the clock signals in such a manner that they overlap one on the other for at least as long as the pulse width of the pulse signal, for example, at least one clock. According to the above arrangement, the pulse signal can be transferred normally between the adjacent blocks. Thus, since an erroneous output of the pulse signal to the latch circuit can be eliminated, the shift register circuit can operate normally, thereby realizing satisfactory video display.
The clock signal may be supplied selectively from the external, but it is preferable to further arrange that a clock signal control circuit for outputting the clock signal to the latch circuits in the block of the shift register circuit for a certain period is provided to each block, and that the clock signal control circuit controls the output of the clock signal based on the output signal from the latch circuits in the preceding and next following blocks.
According to the above arrangement, an additional circuit for controlling the start and end of the output of the clock signal does not have to be provided, because the output of the clock signal is started using the output signal from the latch circuit in the preceding block to the selected block, and the output of the clock signal is stopped using the output signal of the latch circuit in the next following block of the selected block.
Consequently, there can be attained an effect that a circuit added to the data signal line driving circuit can be very small. Moreover, since a control signal for selecting the block is generated inside the data signal line driving circuit, an external terminal for receiving the control signal for selecting the block can be omitted, thereby simplifying the circuit arrangement.
Incidentally, the above-arranged data signal line driving circuit consumes less power and can prevent the time difference between the clock signal and data signal even when a great number of data signal lines are used.
Thus, the above-arranged data signal line driving circuit can be applied to various kinds of apparatuses. Of all the applicable apparatuses, the most preferred example would be an image display apparatus.
To be more specific, the image display apparatus includes a great number of data signal lines and unwanted blur or ghost caused by the time difference readily occurs in the video. However, if the above-arranged data signal line driving circuit is employed as a data signal line driving circuit, the resulting image display apparatus can display a satisfactory image while consuming less power.
For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.